1. Field of the Invention
The present invention relates to data processing systems, and more particularly to an improved execution unit for emulating a function encoded in a stream of microinstructions generated by an instruction unit which decodes macroinstructions and generates said microinstruction stream.
2. Description of the Prior Art
In copending patent application Ser. No. 971,661 of Stephen R. Colley et al, entitled "Data Processing System," filed Dec. 21, 1978, there is disclosed an object-oriented data processor architecture which takes full advantage of recent advances in the stage-of-the-art of very large-scale, integrated-circuit technology. The patent describes a general-purpose processor, which is able to perform generalized computation over a wide spectrum of data types supported by the architecture. Such a complex microprocessor requires a number of complex logical circuits. With present-day integrated-circuit technology, this complex microprocessor is too large to be fabricated on a single chip and therefore, it must be partitioned and fabricated on a number of chips.
In copending patent application of William Richardson, et al entitled "Macroinstruction Unit for Use in a Microprocessor," Ser. No. 119,433 filed on Feb. 7, 1980, several factors are discussed which must be considered in determining where to partition this logic. As described therein, and in the above-identified Colley, et al patent, the microprocessor is partitioned between two chips with an instruction unit on one chip and an execution unit on the other chip. Communication between chips is performed over an interchip bus. Off-chip communication with external devices, such as main memory and input/output devices, is accomplished over an interface more fully described in U.S. Pat. No. 4,315,308 entitled "Microprocessor Interface Control Apparatus" by Daniel K. Jackson, filed on Dec. 21, 1978 which issued on Feb. 9, 1982 and is assigned to Intel Corporation.
The following is a summary of some of the prior approaches to implementing logic for executing microinstructions on an integrated circuit chip.
The Henle, et al U.S. Pat. No. 3,798,606 partitions a computer by splitting up the CPU and memory functions into M modules for processing M bits of data. This patent is representative of bit/slice partitioning techniques which are not utilized in the present invention, which uses a pipeline technique.
The Holmes, Jr., et al U.S. Pat. No. 3,943,494 discloses a microprocessor which is partitioned into a number of synchronized subprocessors each implemented on a separate chip. Each subprocessor has an instruction register and instruction-executing circuits for independently executing a portion of an instruction. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor. This patent does not disclose the concept of partitioning a microprocessor at the instruction unit/execution unit boundary as is done in the present invention. On the contrary, the patent utilizes an instruction register on each subprocessor chip.
In the Watanabe, et al U.S. Pat. No. 3,947,822, a microprocessor is divided into a number of control units such that respective instructions of the control units are executed in a manner to overlap in time. While it discloses a control unit on one chip and a register unit on another chip, it utilizes a time-division control mechanism whereas applicant's invention utilizes a pipelined technique.
The O'Leary U.S. Pat. No. 4,075,704 discloses a pipelined microprocessor. An adder and a multiplier are intercoupled by a number of simultaneously operable parallel buses so that they operate in parallel. The adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock cycle. While this patent discloses a pipelined microprocessor, it does not disclose the partitioning of the microprocessor at the instruction unit/execution unit interface, such as disclosed by the present invention.
It is a primary object of the present invention to provide an execution unit for receiving microinstructions directing said execution unit to perform arithmetic operations and to develop memory addresses from logical addresses contained in said microinstructions.
It is a further object of the present invention to provide an execution unit which is capable of processing variable-length microinstructions received from an instruction unit, and to signal said insturction unit prior to completion of said microinstruction, so that the instruction unit can have a new microinstruction available for execution.
It is also an object of the present invention to provide an execution unit which is so structured that it is able to stop executing an arithmetic operation in order to fetch a macroinstruction from main memory as requested by an instruction unit so that the instruction unit may begin decoding a next macroinstruction while said execution unit is executing the microinstructions comprising a previous macroinstruction.